1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a scan path circuit and a device using the same. More specifically, it relates to an electric system that is designed to facilitate a scan path test with respect to a logic circuit.
2. Description of the Prior Art
FIG. 21 is circuit diagram showing a semiconductor integrated circuit with a scan path circuit as one example of a conventional electric system. In FIG. 21, the reference numeral 1xe2x80x2 designates a scan path circuit; 5xe2x80x2 designates a logic circuit to be tested; 11xe2x80x2-1 to 11xe2x80x2-n each designate a scan register circuit (n=natural number); 13 designates a flip-flop circuit; 17 designates a multiplexer circuit; I11 designates an inverter circuit; and N21, N22 each designate a node.
Such a conventional semiconductor integrated circuit is typically composed of the logic circuit 5xe2x80x2 and scan path circuit 1xe2x80x2. The scan path circuit 1xe2x80x2 is constituted by connecting the plurality of scan register circuits 11xe2x80x2-1 to 11xe2x80x2-n in series, each of which has terminals D1, SI, SM, T on the input side and terminals QC and Q on the output side. As shown in FIG. 21, the scan register circuits 11xe2x80x2-1 to 11xe2x80x2-n each have the flip-flop circuit 13, multiplexer circuit 17, and inverter circuit I11.
Here, the flip-flop circuit 13 has a data input terminal d and a clock terminal t on the input side, and a non-inversion data output terminal q and an inversion data output terminal qc on the output side. The circuit 13 takes in data at the data input terminal d in synchronization with a clock signal through the terminal T of one corresponding scan register circuit, and outputs the data from the non-inversion data output terminal q to the logic circuit 5xe2x80x2 and further outputs the data from the inversion data output terminal qc to the logic circuit 5xe2x80x2 and a scan register circuit at the next stage through the node N21 and terminal Q.
The multiplexer circuit 17 is composed of two OR circuits and one NAND circuit, and selects data at the terminal DI or SI to transfer the data at the terminal d of the flip-flop circuit 13 as a memory circuit. This selection is carried out by a SM signal or shift mode signal through the terminal SM: the terminal SI is selected when the SM signal is xe2x80x9c1xe2x80x9d, while the terminal DI is selected when the SM signal is xe2x80x9c0xe2x80x9d.
Here, the scan path circuit 1xe2x80x2 operates as a serial shift resister in which the terminals SIP and SOP are set at the input and output, respectively when the SM signal is xe2x80x9c1xe2x80x9d, while it operates as a register that takes in from the terminal DI and then outputs the data form the terminals Q and QC.
FIG. 22 is a layout schematic of a semiconductor integrated circuit device employing the semiconductor integrated circuit as shown in FIG. 21. In FIG. 22, the reference numeral 21xe2x80x2 designates a semiconductor integrated circuit device; a1-an, b1-bn, b11-bn1, and b12-bn2 each designate a wire; and N1-Nn each designate a node, and marks which are the same as the above are identified by the same or corresponding parts and these explanation will be omitted. The wires a1-an connects the terminals QC of the scan register circuits 11xe2x80x2-1 to 11xe2x80x2-n to the logic circuit 5xe2x80x2, respectively, while the wires b1-bn are connected to the terminals Q and branch to the wires b11-bn1 and wires b12-bn2 at the node N1-Nn, respectively, and serially connected to the logic circuit 5xe2x80x2 and the scan register circuit at the next stage (e.g., in the case of the scan register circuit 11xe2x80x2-1, the next stage is the scan register circuit 11xe2x80x2-2).
As shown in FIGS. 21 and 22, in the semiconductor integrated circuit with a scan path circuit and the device employing this circuit, a test of the electronic system is carried out by a so-called scan test.
The operation of the scan test will be next described.
In a step ST1, the shift mode signal is set to SM=xe2x80x9c1xe2x80x9d, and test data are serially shifted in from the terminal SIP to the scan path circuit 1xe2x80x2 while a plurality of clock pulses are given to the terminal T of each scan register circuit that is connected to the terminal t of the corresponding flip-flop circuit 13. Subsequently, in a step ST2, it is set to SM=xe2x80x9c0xe2x80x9d, and by supplying one clock pulse to the terminal T, test results of the logic circuit 5xe2x80x2 to the test data are taken in the scan path circuit 1xe2x80x2. Then, in a step ST3, it is set to SM=xe2x80x9c1xe2x80x9d again, and the test results in the scan path circuit 1xe2x80x2 are serially shifted out from the terminal SOP while a plurality of clock pulses are given to the terminal T. Further, in a step ST4, the above steps ST1 to ST3 are repeated. Note that in the step ST3, the operation of the step ST1 also may be simultaneously implemented.
Next, FIG. 23 is a circuit diagram showing one example of a conventional CMOS scan path register circuit, which may be constituted in a CMOS semiconductor circuit device. It should be noted that a connection drawn by a dotted line may be omitted. In FIG. 23, the reference numerals N1-N14, N17, N30, N31 each designate a NMos transistor; and P1-P14, P17, P30, P31 each designate a PMOS transistor. The NMOS transistors N1-N3, N30 and the PMOS transistors P1-P3, P30 constitute a multiplexer circuit 17.
As shown in FIGS. 21 and 23, in many cases, the multiplexer circuit employed in the conventional CMOS scan register circuit is often constituted by employing an OR-NAND compound gate integrated with two OR circuits and one NAND circuit. Here, the compound gate is a function block that is constituted by a combination of a plurality of simple gates such as AND, OR, and inverter. Since this kind of compound gate is commonly optimized when prepared by a vendor, the number of components may be minimized as compared to a case that performs the same function by only simple gates, thereby providing excellent characteristics in consumption power and operating speed.
There is JP-A 06/160479(1994) as a disclosure of a semiconductor integrated circuit prepared with a transfer gate and a latch between an output QC of a flip-flop circuit and a multiplexer circuit at the next stage. In addition, there is JP-A 05/157807(1993) as a memory circuit provided with a transfer gate prepared between an output QC and a multiplexer at the next stage.
Thus, since a scan register circuit is typically provided by a semiconductor or cell library vendor as a simple cell within a cell library in a hierarchy design method, it is common that a flip-flop circuit and a multiplexer circuit in the scan register is fixedly connected with each other.
Since the semiconductor integrated circuit with a scan path circuit and the device using this circuit in the prior art are constituted as, described above, serial wires (Q to SI) for serial shift registers through the nodes N1-Nn are connected to the respective output terminals Q of the scan register circuits 11xe2x80x2-1 to 11xe2x80x2-n constituting the scan path circuit 1xe2x80x2. Since the serial wires become a capacitance element, there arise problems such as delay increase at the output Q and increased consumption power.
The present invention has been implemented to solve the foregoing problems. It is therefore an object to provide a semiconductor integrated circuit and a device with this circuit which prevent delay of an output Q and reduce consumption electric power.
According to a first aspect of the present invention, there is a provided a semiconductor integrated circuit comprising: a scan path circuit being constituted by serially connecting a plurality of scan register circuits, each of which is constituted by an OR-NAND compound gate circuit, a flip-flop circuit, and an OR circuit; and a logic circuit to be tested by use of the scan path circuit, wherein a first input of OR function in the OR-NAND compound circuit is connected to the logic circuit to be tested, and a second input thereof is controlled by a first shift mode signal, while an input of the NAND function is connected to a serial input terminal, and the output thereof is connected to a data input terminal of the flip-flop circuit, and wherein an output of the flip-flop circuit is connected to a first input of the OR circuit, while a second input thereof is controlled by a second shift mode signal, and an output of the OR circuit is connected to a serial output terminal.
Here, the scan register circuits each may include an inverter circuit which outputs a second shift mode signal independent of the scan register circuit in response to the first shift mode signal.
The scan register circuits each may include an inverter circuit which outputs a first shift mode signal independent of the scan register circuit in response to the second shift mode signal.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a scan path circuit being constituted by serially connecting a plurality of scan register circuits, each of which is constituted by an OR-NAND compound gate circuit, a flip-flop circuit, and a NAND circuit; and a logic circuit to be tested by use of the scan path circuit, wherein a first input of OR function in the OR-NAND compound circuit is connected to the logic circuit to be tested, and a second input thereof is controlled by a first shift mode signal, while an input of the NAND function is connected to a serial input terminal, and the output thereof is connected to a data input terminal of the flip-flop circuit, and wherein an output of the flip-flop circuit is connected to a first input of the NAND circuit, while a second input thereof is controlled by a second shift mode signal, and an output of the NAND circuit is connected to a serial output terminal.
Here, the first shift mode signal may be identical to the second shift mode signal.
The flip-flop circuit may have at least two output terminals which output the same logic data, and any one of these terminals is connected to the first input of the NAND circuit.
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit. comprising: a logic circuit to be tested by a scan test; and a scan path circuit being constituted by serially connecting a plurality of scan register circuits, each of which includes a compound gate circuit having a first logic gate and a second logic gate, a flip-flop circuit connecting an output of said compound gate circuit to a data input terminal, and a gate circuit connecting a first input thereof to a data output terminal of the flip-flop circuit and connecting a second input thereof to a second connection terminal input by a second shift mode signal, and which connects the compound gate circuit, flip-flop circuit, and gate circuit in this turn, wherein a first input of the first logic gate is connected to the logic circuit to be tested, and a second input thereof is connected to a first connection terminal input by a first shift mode signal, while a first input of the second logic gate is connected to an output of the first logic gate and a second input thereof is connected to a serial input terminal.
Here, a second input of the second logic gate in the scan register circuit at a first stage may be connected to an output of another gate circuit connecting its first input to one of shift mode signals.
According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device having the above semiconductor integrated circuit,
wherein an output terminal of non-inversion or inversion prepared for the flip-flop circuit is electrically connected to first and second wires which output the same logic data, and the first and second wires electrically connect the circuit to be tested and a first input of the gate circuit in the scan register circuit, respectively.